A commonly used method for forming metal interconnect lines (trenches) and vias in a semiconductor device is known as “damascene”. Generally, this method involves forming an opening in a dielectric layer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional lithographic and etching techniques. After the formation, the opening is filled with copper or copper alloys to form a via or a trench. Excess metal material on the surface of the dielectric layer is then removed by chemical mechanical polish (CMP). The remaining copper or copper alloy forms vias and/or metal interconnect lines.
Copper is typically used in the damascene process because of its lower resistivity. However, copper suffers from electro-migration (EM) and stress-migration (SM) reliability issues, particularly as geometries continue to shrink and current densities continue to increase. Therefore, barrier layers are typically formed to prevent copper from diffusing into neighbouring low-k dielectric materials. Recently, copper silicide nitride layers are increasingly used as barrier layers.
In order to maintain narrow lines reliability performances, Cu/low k interconnect architectures including Self Aligned Barriers on top of Cu lines are widely investigated as an effective solution for the 45 nm generation and beyond. Indeed, electromigration is a major concern for narrow Cu lines coated by dielectric barriers such as SiCN, SiCH and SiCO. Alternative approaches with self aligned barriers are already implemented to improve interconnect performance.
Gosset et al. (Self Aligned Barrier Approach: Overview on Process, Module Integration and Interconnect Performance Improvement Challenges, International Interconnect Technology Conference, 2006 IEEE) describes a self aligned barrier (capping layer) integration, using either a Cu line surface treatment or a selective deposition process on top of the Cu lines. A CuSiN capping layer has been developed for its direct compatibility with existing PE-CVD processes and tools. It consists in a three steps process wherein first the native Cu oxide is removed using reducing plasmas (e.g. H2-based plasmas). In a second step, Cu silicidation, copper is enriched with Si atoms using Si-based precursor decomposition (CVD) such as silane or tri-methyl silane. Finally, a NH3 plasma is performed to achieve the CuSiN self aligned barrier.
Usami et al. (Highly Reliable Interface of Self-aligned CuSiN process with Low-k SiC barrier dielectric (k=3.5) for 65 nm node and beyond, International Interconnect Technology Conference, 2006 IEEE) describes also the deposition of a CuSiN self aligned barrier. In a first step, after planarizing the wafer (Cu-CMP), a reducing plasma was applied to remove surface copper oxide. In a second step, SiH4 gas was exposed on copper surface to diffuse silicon atoms into the copper film. In a third step, post nitrogen containing plasma was applied to scavenge the excess silicon atom and generate Si—N bonds for silicon pinning. Finally, the low k SiC barrier film is deposited on the copper lines. SiC was deposited in a conventional PE-CVD reactor using a more complex organic methyl silane source than the standard precursor used for SiCN (k=4.9) deposition.
In U.S. Pat. No. 6,821,890 a process is disclosed to provide an intervening capping layer of copper germanide, germanide oxide, germanium nitride or combinations thereof to improve adhesion of poorly adhering material onto the copper surface.
The conventional formation process of barrier layers such as copper silicide still suffers from drawbacks. Since copper silicide is relatively unstable, silicon may still break from copper silicide and diffuse into low-k dielectric layer. Therefore, it is preferred that copper silicide layer is fully nitrated to form copper silicide nitride, which is more stable. This requires long NH3 plasma treatment and/or high power. However, plasma treatments have the side effect of incurring damage to low-k dielectric layer.
The use of copper germanide as a capping layer has the advantage of being more stable and having a lower resistivity. However, copper germanide (and nitrided copper germanide) suffers from worse electromigration performance compared to a (nitrided) copper silicide capping layer.